1. Field
Example embodiments relate to a charge pump circuit, and more particularly, to a charge pump circuit and method of controlling the same to address activation issues relating to a parasitic transistor. Example embodiments of a charge pump and related methods do not use a Schottky diode.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional charge pump circuit 100.
Referring to FIG. 1, the conventional charge pump circuit 100 includes a regulator 110, a first charge pump 120, a second charge pump 130, and a booster 140. The regulator 110 regulates an input signal IN to a first output signal OUT_1 at a first voltage VCI1, and transmits the first output signal OUT_1 to the first charge pump 120, the second charge pump 130, and the booster 140. In response to the first output signal OUT_1, the first charge pump 120 outputs a second output signal OUT_2 at a second voltage AVDD. The second voltage AVDD may be twice as large as the positive value of the first voltage VC1, for example. In response to the first output signal OUT_1, the second charge pump 130 outputs a third output signal OUT_3 at a third voltage—VCI1. In response to the first output signal through the third output signal OUT_1, OUT_2, and OUT_3, the booster 140 outputs a fourth output signal OUT_4 at a fourth voltage VGH and a fifth output signal OUT_5 at a fifth voltage VGL. The fourth voltage VGH may be a positive value about four to five times as larger than a positive value of the first voltage VCI1, and the fifth voltage VGL may be a negative value that is three through to six times larger than the positive first voltage VCI1. In order to activate a liquid crystal panel, a semiconductor integrated circuit may use the fourth output signal OUT_4 or the fifth output signal OUT_5 output from the charge pump circuit 100.
FIG. 2 is a waveform diagram illustrating the output signals OUT_1, OUT_2, OUT_4, and OUT_5 of the conventional charge pump circuit 100 shown in FIG. 1
Referring to FIGS. 1 and 2, a parasitic transistor substantially, instantaneously turns on when the first output signal OUT_1 is regulated at the first voltage VCI1, and the second output signal OUT_2 is charged at a ground voltage VSS. The parasitic transistor also turns on when the fourth output signal OUT_4 is boosted from the ground voltage VSS, which may cause a latch-up operation.
FIG. 3 is a diagram illustrating a parasitic transistor generated in the case where the conventional charge pump circuit 100 shown in FIG. 1 is formed on a semiconductor substrate.
Referring to the conventional configuration of FIG. 3, when the first output signal OUT_1 is regulated, the regulator 110 operates faster than the fourth output signal OUT_4 is charged so that a PNP bipolar junction transistor substantially, instantaneously turns on. When the second output signal OUT_2 is boosted, the second output signal OUT_2 is boosted faster than the fourth output signal OUT_4 is charged so that the PNP bipolar junction transistor turns on. Also, when the fourth output signal OUT_4 is charged, the first output signal OUT_1 or the second output signal OUT_2 is boosted faster than the fourth output signal OUT_4 is charged so that the PNP bipolar junction transistor and an NPN bipolar junction transistor turn on thereby performing a latch-up operation.
FIGS. 4A and 4B are circuit diagrams illustrating conventional technology for addressing issues and/or solving problems caused by a parasitic transistor such as is shown in FIG. 3, for example.
Referring to FIG. 4A, conventionally, a problem caused by the parasitic transistor is solved by attaching an external Schottky diode to a PNP bipolar junction transistor. That is, when the PNP bipolar junction transistor turns on, current i flows to the external Schottky diode via the PNP bipolar junction transistor.
Referring to FIG. 4B, similar to that shown in FIG. 4A, an external Schottky diode is attached to a circuit which performs a latch-up operation, so as to solve the problem caused by the parasitic transistor. That is, in the case where there is no external Schottky diode both the PNP bipolar junction transistor and an NPN bipolar junction transistor turn on so that the circuit shown in FIG. 4B performs a latch-up operation. However, the latch-up operation is prevented by attaching the external Schottky diode to the circuit so that current i flows to the external Schottky via the PNP bipolar junction transistor diode.
However, in the case where the external Schottky diode is used as described above, additional components must be attached to the semiconductor device, thereby increasing cost.